To protect an integrated circuit (IC) from static electricity, an electrostatic discharge (ESD) protection circuit may be used. A high-voltage IC which uses a high driving voltage and operates in an environment sensitive to static electricity requires a higher level of ESD protection than that of a general logic IC.
FIG. 1A shows the configuration of an ESD protection circuit using a general Laterally Diffused Metal Oxide Semiconductor (LDMOS) device. Referring to FIG. 1A, an ESD circuit 110 and an internal circuit 120 are connected in parallel between a first pad 105, to which a driving voltage VDD is applied from an external device, and a second pad 107, to which a ground voltage VSS is applied. The ESD circuit 110 is a grounded-gate LDMOS device.
FIG. 1B shows a current-voltage curve of the grounded-gate LDMOS 110 shown in FIG. 1A. The current-voltage curve S1 represents characteristics when static electricity is applied to the first pad 105 or the second pad 107. Referring to FIG. 1B, noise or glitches due to static electricity are introduced from an external device into the first pad 105. Therefore, when the grounded-gate LDMOS 110 is operated, a latch-up phenomenon, wherein the grounded-gate LDMOS 110 is not turned off even when the static electricity is no longer present, is generated.
This is because the sustaining voltage or the snapback voltage Vsp of the grounded-gate LDMOS 110 is lower than the driving voltage VDD of the internal circuit 120, as shown in FIG. 1B. Due to the latch-up phenomenon, the grounded-gate LDMOS 110 breaks down. As a result, this may lead to breakdown of the internal circuit 120.
A high-voltage diode may be used as the ESD protection circuit. The high-voltage diode does not generate the above-described latch-up phenomenon, but occupies a large area. Thus, the high-voltage diode is not suitable for an IC.